Method of forming finfet having fins of different height

ABSTRACT

A device is fabricated on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. A first mask is formed over the surface at a first portion of the wafer, leaving a second portion of the wafer unmasked. The wafer is etched at the unmasked second portion of the wafer to form a depression in the active silicon layer. A thermal oxide layer is formed to substantially fill the depression, the first mask is removed, and fins are formed at the first and second portions of the wafer.

CLAIM OF PRIORITY UNDER 35 USC §120

The present Application for Patent is a divisional application of andclaims priority to application Ser. No. 13/784,867, entitled “METHOD OFFORMING FINFET HAVING FINS OF DIFFERENT HEIGHT,” filed Mar. 5, 2013, andassigned to the assignee hereof and hereby expressly incorporated byreference herein.

FIELD OF THE DISCLOSURE

The present disclosure is directed to a method of forming a finned fieldeffect transistor (finFET) having fins of different height and toward afinFET formed thereby, and, more specifically, toward a method offorming a finFET on a silicon-on-insulator (SOI) substrate which methodincludes etching a depression in a surface of the SOI substrate andforming an oxide layer in the etched depression and toward a finFETformed thereby.

BACKGROUND

A finned field effect transistor (finFET) is a FET that includes afin-shaped channel region. A gate structure intersects the channelregion, and the ends of the fin structure receive source and draindoping. The dimensions of the fin affect the operation of a finFET. Forexample, the length of the fin under the gate, measured in the directionfrom source to drain, determines the effective channel length of thedevice. It is desirable to form fins having a consistent height, andforming a finFET on a silicon-on-insulator (SOI) wafer provides improvedfin height uniformity. This improved uniformity may be important as finheight scales.

For various applications, including system on chip (SOC) operation, itis useful to make finFETs with fins having at least two differentheights. When bulk silicon is used, fin height can be controlled byremoving different amounts of the shallow trench isolation (STI) oxidelayer around different groups of fins. Essentially, all fins have thesame height when measured from the underlying silicon layer, butdifferent amounts of the STI oxide region are left around different finsso that different heights of the fins are left projecting from the STIlayer. However, when an SOI wafer is used, the thickness of the siliconlayer is predetermined, and the conventional method cannot be usedwithout modification to achieve different fin heights. Instead, it maybe necessary to form an STI layer on the SOI active silicon layer, maskthe area over a fin that is to be a shorter fin and selectively etch theSTI layer around another fin to form a taller fin, which is similar tothe method used in bulk substrate and that undermines the intendedbenefit of finFET on SOI substrate.

Another known method for forming a finFET on an SOI wafer with finshaving different heights is illustrated in FIGS. 1-6. FIG. 1 illustratesa conventional SOI wafer 100 that includes a substrate 102, a bottomoxide (BOX) layer 104 and an active silicon layer 106 having a topsurface 108. In FIG. 2, a hardmask 202, which may comprise siliconnitride, for example, is formed on the top surface 108, and a patternedresist 204 is formed on the hardmask so that a first portion 206 of theSOI wafer 100 is masked and a second portion 208 of the SOI wafer 100 isnot masked. In FIG. 3, the portion of the hardmask 202 that is notprotected by the resist 204 is etched down to the top surface 108. Withthe top surface 108 exposed and the first portion 206 of the SOI wafer100 protected, the top surface 108 is oxidized to form a depression 402filled with a top oxide layer 404 as illustrated in FIG. 4. Theoxidation process produces a generally symmetric oxide layer 404 whichprojects upwardly beyond the top surface 108 of the active silicon layer106 about as far as it projects downwardly into the active silicon layer106.

FIG. 5 shows the SOI wafer 100 after the hardmask 202 and patternedresist 204 have been removed at which time a first plurality of masks502 are formed in the first portion 206 of the SOI wafer 100 and asecond plurality of masks 504 are formed in the second portion 208 ofthe SOI wafer 100 on the top oxide layer 404. The silicon not protectedby the first plurality of masks 502 in the first portion 206 and thesilicon and oxide not protected by the second plurality of masks 504 inthe second portion 208 are etched away to produce a plurality of fins.FIG. 6 illustrates a first plurality of fins 602 in the first portion206 of the SOI wafer 100 that are taller than a second plurality of fins604 in the second portion 208 of the SOI wafer 100. While this methodmay produce fins for a finFET that are acceptable for some applications,the uneven top surface created by the top oxide layer 404 protrudingfrom the top surface 108 of the active silicon layer 106 may make itdifficult to apply masks for later forming the first and secondplurality of fins.

It would therefore be desirable to provide a method of forming fins onan SOI wafer that have different heights in a manner that does notrequire the addition of an STI layer to the SOI wafer and that providesa substantially even surface on which to form a mask for forming thedifferent height fins.

SUMMARY

A first exemplary embodiment of the invention comprises an SOI waferhaving a silicon layer having a top surface, the SOI wafer having afirst portion and a second portion. The second portion includes anetched depression having an oxidized bottom and an oxide layer in theetched depression having an oxide layer top surface, where the oxidelayer top surface is substantially even with the silicon layer topsurface. The device also includes a plurality of mask portions on thesilicon layer top surface and on the oxide layer top surface fordefining a first plurality of fins at the first SOI wafer portion and asecond plurality of fins at the second SOI wafer portion.

A further exemplary embodiment comprises a non-transient computerreadable medium containing instructions that, when executed by acomputer processor cause a device controlled by the computer processorto perform actions on an silicon SOI wafer comprising a substrate, abottom oxide layer on the substrate and an active silicon layer on thebottom oxide layer, the active silicon layer having a surface oppositethe bottom oxide layer. The actions include forming a first mask overthe surface at a first portion of the wafer and leaving a second portionof the wafer unmasked, etching the wafer at the unmasked second portionof the wafer to form a depression in the active silicon layer, thedepression having a bottom, forming a thermal oxide layer substantiallyfilling the depression, removing the first mask and forming fins at thefirst and second portions of the wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are presented to aid in the description ofembodiments of the invention and are provided solely for illustration ofthe embodiments and not limitation thereof.

FIGS. 1-6 are schematic side elevational views of a silicon-on-insulator(SOI) wafer as various conventional processes are performed thereon toform fins having different heights.

FIGS. 7-12 are schematic side elevational views of an SOI wafer asvarious processes according to an embodiment of the disclosure areperformed thereon to form fins having different heights.

FIG. 13 is a flow chart illustrating a method according to anembodiment.

FIG. 14 is a schematic diagram of an exemplary wireless communicationsystem in which embodiments of the disclosure may be used.

DETAILED DESCRIPTION

Aspects of the invention are disclosed in the following description andrelated drawings directed to specific embodiments of the invention.Alternate embodiments may be devised without departing from the scope ofthe invention. Additionally, well-known elements of the invention willnot be described in detail or will be omitted so as not to obscure therelevant details of the invention.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any embodiment described herein as“exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments. Likewise, the term “embodiments ofthe invention” does not require that all embodiments of the inventioninclude the discussed feature, advantage or mode of operation.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of embodiments ofthe invention. As used herein, the singular forms “a,” “an” and “the”are intended to include the plural forms as well, unless the contextclearly indicates otherwise. It will be further understood that theterms “comprises,” “comprising,” “includes,” and/or “including,” whenused herein, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

Further, many embodiments are described in terms of sequences of actionsto be performed by, for example, elements of a computing device. It willbe recognized that various actions described herein can be performed byspecific circuits (e.g., application specific integrated circuits(ASICs)), by program instructions being executed by one or moreprocessors, or by a combination of both. Additionally, these sequence ofactions described herein can be considered to be embodied entirelywithin any form of computer readable storage medium having storedtherein a corresponding set of computer instructions that upon executionwould cause an associated processor to perform the functionalitydescribed herein. Thus, the various aspects of the invention may beembodied in a number of different forms, all of which have beencontemplated to be within the scope of the claimed subject matter. Inaddition, for each of the embodiments described herein, thecorresponding form of any such embodiments may be described herein as,for example, “logic configured to” perform the described action.

FIG. 7 illustrates an SOI wafer 700 that includes a substrate 702, abottom oxide layer 704 and an active silicon layer 706 having a topsurface 708. In FIG. 8, a hardmask 802, which may comprise siliconnitride, is formed on the top surface 708, and a patterned resist 804 isformed on the hardmask 802 so that a first portion 806 of the SOI wafer700 is masked and a second portion 808 of the SOI wafer 700 is notmasked. An etching process, which may comprise a dry etching processusing, for example, an etchant gas containing F, Br, or Cl such as SF₆,HBr, and Cl₂, or a wet etching process, for example, using EDP(EthyleneDiamine Pyrocatechol), KOH, TMAH (Tetramethyl ammoniumhydroxide), or mixture of HF+HNO₃+CH₃COOH, or a dry etch followed by awet etch, is then performed. This etches away the exposed hardmask 802in the second portion 808 of the wafer and, in addition, as illustratedin FIG. 9, etches a depression 902 having a bottom 904 in the topsurface 708 of the active silicon layer 706 of the SOI wafer 700. Thisetching process is not an oxidation process, but rather a process ofphysically or chemically removing a portion of the active silicon layer706 in the second portion 808 of the SOI wafer 700 in preparation for asubsequent oxidation process discussed below.

After the aforementioned etching process, the bottom 904 of thedepression 902 is oxidized as illustrated in FIG. 10 with an oxidationprocess that forms a thermal oxide layer 1002 and which process deepensthe depression 902, forming a new bottom 1004 of the depression 902closer to the bottom oxide layer 704. The bottom 904 of the depression902 as it existed before the oxidation process is illustrated in FIG. 10with dashed lines. The oxidation process produces a generally symmetricthermal oxide layer 1002, and the thermal oxide layer 1002 growsupwardly at about the same rate as the depth of the depression 902increases. The oxidation process is stopped when the top surface 1006 ofthe thermal oxide layer 1002 is generally even with the top surface 708of the active silicon layer 706 and when the depression 902 issubstantially filled with the thermal oxide layer 1002. Next thepatterned resist 804 is removed, for example, by an oxygen based ashingprocess or wet cleaning such as SPM (Sulfuric Peroxide Mixture) ormixture of both ashing and wet clean, and the hardmask 802 is removed,for example, by hot phosphorous acid. This exposes the top surface 708of the active silicon layer 706 and the top surface 1006 of the thermaloxide layer 1002 which together provide a substantially level surfacefor the subsequent formation of additional masks for forming fins.

FIG. 11 illustrates a plurality of first masks 1102 formed on the topsurface 708 of the active silicon layer 706 in the first portion 806 ofthe SOI wafer 700 and a plurality of second masks 1104 formed on the topsurface 1106 of the thermal oxide layer 1002. These first and secondmasks 1102, 1104 define the locations and desired widths of a pluralityof fins that will be formed beneath each of the masks 1102, 1104 duringa further processing step in which the portions of the active siliconlayer 706 that are not beneath a first mask 1102 or a second mask 1104and the portions of the thermal oxide layer 1002 that are not beneath asecond mask 1104 are removed. The result, as illustrated in FIG. 12, isa plurality of first fins 1202 beneath each of the plurality of firstmasks 1102 and a plurality of second fins 1204 beneath each of theplurality of second masks 1104 which second fins 1204 are shorter thanthe plurality of first fins 1202. A finFET is formed from thesedifferent-height fins in a conventional manner. Beneficially, theforegoing method produces a substantially level surface, comprising thetop surface 708 of the active silicon region and the top surface 1006 ofthe thermal oxide layer 1002, on which the first and second plurality ofmasks 1102 and 1104 can then be formed. This smooth surface may lead tomore accurate mask placement and better consistency in the heights ofthe first plurality of fins 1202 and in the heights of the secondplurality of fins 1204. For example, considering a process integrationflow that maintains the thermal oxide layer 1002 on top of the shortfins 1204 in a downstream process, aligned fin height makes processintegration such as gate etch and spacer etch easier due to one singleaspect ratio of the fins themselves (including thermal oxide layer 1002)and also fin-to-fin space aspect ratio.

FIG. 13 illustrates a method according to an embodiment that includes ablock 1302 of providing a silicon-on-insulator (SOI) wafer comprising asubstrate, a bottom oxide layer on the substrate and an active siliconlayer on the bottom oxide layer, where the active silicon layer has asurface opposite the bottom oxide layer. The method also includes ablock 1304 of forming a first mask over the surface at a first portionof the wafer and leaving a second portion of the wafer unmasked, and ablock 1306 of etching the wafer at the unmasked second portion of thewafer to form a depression in the active silicon layer, the depressionhaving a bottom. In addition, the method includes a block 1308 offorming a thermal oxide layer substantially filling the depression, ablock 1310 of removing the first mask, and a block 1312 of forming finsat the first and second portions of the wafer.

FIG. 14 illustrates an exemplary wireless communication system 1400 inwhich one or more embodiments of the disclosure may be advantageouslyemployed. For purposes of illustration, FIG. 14 shows three remote units1420, 1430, and 1450 and two base stations 1440. It will be recognizedthat conventional wireless communication systems may have many moreremote units and base stations. The remote units 1420, 1430, and 1450include integrated circuit or other semiconductor devices 1425, 1435 and1455 (including finFET's with fins of different height as disclosedherein), which are among embodiments of the disclosure as discussedfurther below. FIG. 14 shows forward link signals 1480 from the basestations 1440 and the remote units 1420, 1430, and 1450 and reverse linksignals 1490 from the remote units 1420, 1430, and 1450 to the basestations 1440.

In FIG. 14, the remote unit 1420 is shown as a mobile telephone, theremote unit 1430 is shown as a portable computer, and the remote unit1450 is shown as a fixed location remote unit in a wireless local loopsystem. For example, the remote units may be any one or combination of amobile phone, hand-held personal communication system (PCS) unit,portable data unit such as a personal digital or data assistant (PDA),navigation device (such as GPS enabled devices), set top box, musicplayer, video player, entertainment unit, fixed location data unit suchas meter reading equipment, or any other device that stores or retrievesdata or computer instructions, or any combination thereof. Although FIG.14 illustrates remote units according to the teachings of thedisclosure, the disclosure is not limited to these exemplary illustratedunits. Embodiments of the disclosure may be suitably employed in anydevice having active integrated circuitry including memory and on-chipcircuitry for test and characterization.

Those of skill in the art will appreciate that information and signalsmay be represented using any of a variety of different technologies andtechniques. For example, data, instructions, commands, information,signals, bits, symbols, and chips that may be referenced throughout theabove description may be represented by voltages, currents,electromagnetic waves, magnetic fields or particles, optical fields orparticles, or any combination thereof.

Further, those of skill in the art will appreciate that the variousillustrative logical blocks, modules, circuits, and algorithm stepsdescribed in connection with the embodiments disclosed herein may beimplemented as electronic hardware, computer software, or combinationsof both. To clearly illustrate this interchangeability of hardware andsoftware, various illustrative components, blocks, modules, circuits,and steps have been described above generally in terms of theirfunctionality. Whether such functionality is implemented as hardware orsoftware depends upon the particular application and design constraintsimposed on the overall system. Skilled artisans may implement thedescribed functionality in varying ways for each particular application,but such implementation decisions should not be interpreted as causing adeparture from the scope of the present invention.

The methods, sequences and/or algorithms described in connection withthe embodiments disclosed herein may be embodied directly in hardware,in a software module executed by a processor, or in a combination of thetwo. A software module may reside in RAM memory, flash memory, ROMmemory, EPROM memory, EEPROM memory, registers, hard disk, a removabledisk, a CD-ROM, or any other form of storage medium known in the art. Anexemplary storage medium is coupled to the processor such that theprocessor can read information from, and write information to, thestorage medium. In the alternative, the storage medium may be integralto the processor.

Accordingly, an embodiment of the invention can include a computerreadable media embodying a method for forming a finFET having fins withdifferent heights. Accordingly, the invention is not limited toillustrated examples and any means for performing the functionalitydescribed herein are included in embodiments of the invention.

While the foregoing disclosure shows illustrative embodiments of theinvention, it should be noted that various changes and modificationscould be made herein without departing from the scope of the inventionas defined by the appended claims. The functions, steps and/or actionsof the method claims in accordance with the embodiments of the inventiondescribed herein need not be performed in any particular order.Furthermore, although elements of the invention may be described orclaimed in the singular, the plural is contemplated unless limitation tothe singular is explicitly stated.

What is claimed is:
 1. A device comprising: an SOI wafer having asilicon layer having a top surface, the SOI wafer having a first portionand a second portion, the second portion including an etched depressionhaving an oxidized bottom; an oxide layer in the etched depressionhaving an oxide layer top surface, the oxide layer top surface beingsubstantially even with the silicon layer top surface; and a pluralityof mask portions on the silicon layer top surface and on the oxide layertop surface for defining a first plurality of fins at the first SOIwafer portion and a second plurality of fins at the second SOI waferportion.
 2. The device of claim 1, including a first plurality ofsilicon fins beneath each of the plurality of mask portions and a secondplurality of silicon fins beneath each of the plurality of second maskportions.
 3. The device of claim 2, wherein a height of the firstplurality of fins is greater than a height of the second plurality offins.
 4. The device of claim 3 incorporated into at least onesemiconductor die.
 5. The device of claim 1, wherein the device isselected from the group consisting of a set top box, a music player, avideo player, an entertainment unit, a navigation device, acommunications device, a personal digital assistant (PDA), a fixedlocation data unit, and a computer.
 6. A non-transient computer readablemedium containing instructions that, when executed by a computerprocessor cause a device controlled by the computer processor to performactions on an SOI wafer comprising a substrate, a bottom oxide layer onthe substrate and an active silicon layer on the bottom oxide layer, theactive silicon layer having a surface opposite the bottom oxide layer,the actions including: forming a first mask over the surface at a firstportion of the wafer and leaving a second portion of the wafer unmasked;etching the wafer at the unmasked second portion of the wafer to form adepression in the active silicon layer, the depression having a bottom;forming a thermal oxide layer substantially filling the depression;removing the first mask; and forming fins at the first and secondportions of the wafer.
 7. The non-transient computer readable medium ofclaim 6, the actions further including, before forming the first mask,forming a hardmask over the surface and wherein etching the wafer at theunmasked second portion comprises etching through the hardmask and intothe active silicon layer.
 8. The non-transient computer readable mediumof claim 6, wherein forming a thermal oxide layer substantially fillingthe depression comprises forming a thermal oxide layer filling thedepression to a level substantially even with the surface.
 9. Thenon-transient computer readable medium of claim 6, wherein forming finscomprises forming a first plurality of second masks on the surface atthe first portion of the wafer, forming a second plurality of secondmasks on the thermal oxide layer and patterning the wafer to removeportions of the silicon layer not protected by the first plurality ofsecond masks or the second plurality of second masks.
 10. Thenon-transient computer readable medium of claim 6, wherein forming athermal oxide layer comprises oxidizing the bottom of the depression.11. The non-transient computer readable medium of claim 6, the actionsfurther including, before forming the first mask, forming a hardmaskover the surface, and wherein etching the wafer at the unmasked secondportion comprises etching through the hardmask and into the activesilicon layer, wherein forming a thermal oxide layer comprises oxidizingthe bottom of the depression until a thermal oxide layer on the bottomof the depression is substantially even with the surface and whereinforming fins comprises forming a first plurality of second masks on thesurface at the first portion of the wafer, forming a second plurality ofsecond masks on the thermal oxide layer and patterning the SOI wafer toremove portions of the silicon layer not protected by the firstplurality of second masks or the second plurality of second masks. 7.The non-transient computer readable medium of claim 6, wherein formingfins at the first and second portions of the wafer comprises formingfins having a first height at the first portion of the wafer and formingfins having a second height, less than the first height, at the secondportion of the wafer.
 8. The non-transient computer readable medium ofclaim 6, wherein etching the surface comprises performing a wet etch orperforming a dry etch or performing both a wet etch and a dry etch. 9.The non-transient computer readable medium of claim 6, the actionsfurther including forming a finFET device using the fins.